Successive approximation register (SAR) analog to digital converters (ADCs) convert an analog signal into a digital code representing the signal's voltage. In some instances, these bits may be resolved sequentially from the most significant bit (MSB) to the least significant bit (LSB) using an array of typically binary weighted capacitors. Ordinarily, each bit is represented by a single capacitor, with the capacitor's size weighted to correspond to its respective bit. For a capacitor at an ith bit, the capacitor generally is sized to 2i-1·CLSB, where CLSB is the size of a capacitor at the least significant bit. To achieve conversion, the analog signal may be coupled initially to each of the capacitors for a predetermined time to allow the signal to be sampled. After this time has elapsed, the capacitors may be decoupled from the analog signal and coupled to a comparator input. Each of the weighted capacitors may then be coupled iteratively to a reference voltage to incrementally adjust the voltage at the comparator input along with capacitors of any bits of previous iterations. This adjusted voltage at the comparator input may then be compared to the reference voltage each time another weighted capacitor is coupled to the reference voltage in order to calculate each bit of the converted digital output signal.
Resolution can be improved by adding additional weighted capacitors to calculate additional bits. However, as the number of weighted capacitors increases, the circuit becomes more sensitive to manufacturing defects and variations that effectively cause static radix deviation. To account for the effects of these defects and variations, an ADC operating at higher resolutions may be calibrated.
Typically, calibration occurs by relying on an initial set of pre-calibrated capacitors or other assumed-ideal converter elements associated with a group of LSBs to calibrate the next converter element or capacitor in the sequence by comparing the effects of each on the converter output. Once a capacitor has been calibrated, the calibrated capacitor may then be used to calibrate the next uncalibrated capacitor in the sequence, and so on. However, this calibration technique will only work if the aggregate maximum voltage generated from charge stored in each of the previously calibrated or assumed-ideal capacitors is greater than or equal to that of the capacitor to be calibrated.
This may not always be the case. For example, manufacturing defects and variances may cause the capacitor to be calibrated to exceed its nominal value and therefore exceed the measureable voltage of the previously calibrated capacitors and reference capacitors. To avoid this, manufacturers often include additional reference capacitors to increase the maximum measureable voltage. While these additional capacitors may be used during calibration, the additional capacitors need not be used during runtime. This leads to an inefficient use of resources during runtime, as power, area, and other resources may be diverted to these additional capacitors even though the capacitors are not needed.
Some of these inefficient configurations include: adding additional redundant capacitors in the ADC, using non-radix-2 bit stages, and using one or more tunable capacitors that may be adjusted to account for any deviations. In other circuit configurations, an additional ADC circuit has been added to assist in capacitor calibration and provide sufficient signal range when measuring capacitor manufacturing deviations. A least-mean-square (LMS) loop has also been used to estimate manufacturing deviations. Each of these configurations may require additional time for signal processing during conversion, may consume additional power, may require additional space to house the added circuitry, and/or may decrease the signal-to-noise ratio.
The inventors perceive a need for more efficient ADC calibration methods and apparatuses that do not result in excess and unused resources.